1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically to a semiconductor integrated circuit device suitable to control the threshold value thereof for power reduction at standby time.
2. Description of the Prior Art
In general, one of the effective methods of reducing the power consumption of a semiconductor integrated circuit device including MOSFETs, in particular of a CMOS integrated circuit is to reduce the supply voltage thereof. When the supply voltage is reduced, however, the operating speed of the CMOS circuit inevitably decreases.
Therefore, when not only the supply voltage but also the threshold value are both reduced, it is possible to reduce the power consumption at operation time without decreasing the circuit operating speed. In this case, however, when the threshold value is reduced, since the subthreshold current of the MOSFET increases at standby time, the consumption power increases at standby time. Therefore, it is desirable to keep the threshold value high at standby time but low at operation time.
The threshold value of the MOSFET is modulated by the substrate potential (back gate effect). Therefore, when a bias voltage is applied to the substrate (a potential lower than the source is applied in an NMOS but a potential higher than the source is applied in a PMOS), the threshold value can be increased. Therefore, a technique for controlling the threshold value of the MOSFET by utilization of this phenomenon has been developed, as disclosed by a reference document 1: K. Seta, et al., xe2x80x9c50% Active-Power Saving without Speed Degradation using Stand-by Power Reduction (SPR) Circuitxe2x80x9d ISSCC Digest of Technical Papers, pp. 318-319, February, 1995.
FIG. 16 shows the construction of a threshold value control circuit as disclosed by this reference document 1, in which the threshold value is switched from the standby time to the operation time or vice versa. For instance, at standby time, xe2x88x922V is applied to a P well or a P type substrate (referred to as a P-type semiconductor substrate), and 4V is applied to an N well or an N type substrate (referred to as an N-type semiconductor substrate). Further, at operation time, 0V is applied to the P-type semiconductor substrate and 2V is applied to the N-type semiconductor substrate.
In the above-mentioned circuit as shown in FIG. 16, however, two new supply voltages VPBB (=xe2x88x922V) and VNBB (=4V) are necessary in addition to a drive supply voltage VDD (=2V) and a ground supply voltage GND (=0V).
Further, in the circuit as shown in FIG. 16, the substrate terminal of an NMOSFET is connected to the supply voltage GND; the substrate terminal of another NMOSFET is connected to the supply voltage VPBB; the substrate terminal of a PMOSFET is connected to the supply voltage VDD; and the substrate terminal of another PMOSFET is connected to the supply voltage VNBB, so that a triple-well structure is required, thus causing a problem in that the manufacturing process inevitably increases.
With these problems in mind, therefore, it is the object of the present invention to provide a semiconductor integrated circuit device which can control the threshold value thereof, without use of any supply voltages other than the drive and ground supply voltages.
To achieve the above-mentioned object, the first aspect of the present invention provides a semiconductor integrated circuit device, comprising: a substrate potential generating circuit operative on the basis of a control signal, for deepening a substrate bias by pumping out charges from a semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; and a switch circuit operative on the basis of the control signal and turned on when said substrate potential generating circuit is deactivated, to set potential of the semiconductor substrate to a supply potential, but turned off when said substrate potential generating circuit is activated.
Further, the second aspect of the present invention provides a semiconductor integrated circuit device, comprising: a substrate potential detecting circuit for detecting potential of a semiconductor substrate; a substrate potential generating circuit for deepening a substrate bias by pumping out charges from the semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; a switch circuit turned on when said substrate potential generating circuit is deactivated, to connect the semiconductor substrate to a supply voltage, but turned off when said substrate potential generating circuit is activated; and a control circuit for driving said substrate potential generating circuit and said switch circuit on the basis of a control signal, a value detected by said substrate potential detecting circuit, and a set value, to control the potential of the semiconductor substrate to the set value or a potential of the supply voltage.
Further, the third aspect of the present invention provides a semiconductor integrated circuit device, comprising: a leak current detecting circuit for detecting leak current of a transistor formed on a semiconductor substrate; a substrate potential generating circuit for deepening a substrate bias by pumping out charges from the semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; a switch circuit turned on when said substrate potential generating circuit is deactivated, to connect the semiconductor substrate to a supply voltage, but turned off when said substrate potential generating circuit is activated; and a control circuit for driving said substrate potential generating circuit and said switch circuit on the basis of a control signal, a value detected by said substrate potential detecting circuit and a set value, to control the potential of the semiconductor substrate to the set value or a potential of the supply voltage.
Further, the fourth aspect of the present invention provides a semiconductor integrated circuit device, comprising: a first pump circuit having an output terminal connected to a first-conductivity type semiconductor substrate, for pumping out first-conductivity type carriers; a first MOSFET with a second-conductivity type different from the first-conductivity type having a source terminal connected to the output terminal of said first pump circuit and a drain terminal connected to a first supply voltage; a second pump circuit having an output terminal connected to a gate terminal of the first MOSFET, for pumping out first-conductivity type carriers; and a second MOSFET with the first-conductivity type having a source terminal connected to a second supply voltage, a gate terminal to which a control signal is applied, and a drain terminal connected to the gate terminal of said first MOSFET.
Further, it is preferable that the semiconductor integrated circuit device further comprises first and second rectifying circuits connected between the gate and source terminals of said first MOSFET in such a way that polarity thereof is inverse parallel to each other.
Further, it is preferable that the semiconductor substrate is of P-type semiconductor substrate; said first MOSFET is an N-channel MOSFET; said second MOSFET is a P-channel MOSFET; the first supply voltage is a ground supply voltage, and the second supply voltage is a drive supply voltage.
Further, it is preferable that the semiconductor substrate is of N-type semiconductor substrate; said first MOSFET is a P-channel MOSFET; said second MOSFET is an N-channel MOSFET; the first supply voltage is a ground supply voltage, and the second supply voltage is a drive supply voltage.
Further, it is preferable that the semiconductor integrated circuit device further comprises a third MOSFET with the first-conductivity type having a gate terminal connected to the first supply voltage and connected between the drain terminal of said second MOSFET and the gate terminal of said first MOSFET.
Further, it is preferable that the semiconductor substrate is of P-type semiconductor substrate; said first MOSFET is an N-channel MOSFET; said second and third MOSFETs are P-channel MOSFETs; the first supply voltage is a ground supply voltage, and the second supply voltage is a drive supply voltage.
Further, it is preferable that the semiconductor integrated circuit device further comprises an N-channel MOS having a gate terminal connected to the ground supply voltage, and connected between the source terminal of said first MOSFET and an output terminal of one of said two rectifying circuits, for passing current from the gate terminal to the source terminal of said first MOSFET.
Further, it is preferable that the semiconductor substrate is of N-type semiconductor substrate; said first MOSFET is a P-channel MOSFET; said second and third MOSFETs are N-channel MOSFETs; the first supply voltage is a drive supply voltage, and the second supply voltage is a ground supply voltage.
Further, it is preferable that the semiconductor integrated circuit device further comprises a P-channel MOS having a grounded gate terminal connected to the drive supply voltage, and connected between the source terminal of said first MOSFET and an input terminal of one of said two rectifying circuits, for passing current from the source terminal to the gate terminal of said first MOSFET.
Further, it is preferable that each of said first and second rectifying circuits is composed of a single diode element or a plurality of series-connected diode elements.